This invention relates to a code converting circuit which converts fixed length codes into variable length codes and delivers out a resultant train of variable length codes every K (constant) bits.
For the PCM transmission of signals of a wide bandwidth such as video signals, the concept of lowering the transmission bit rate by converting fixed length codes into variable length codes has been conceived. With the variable length code scheme, the overall bit rate can be drastically lowered by, for example, allocating bits of a short length to codes of frequent occurrence. Practical hardware for this purpose, however, calls for a complicated, large-scale circuitry as disclosed in U.S. Pat. No. 4,276,544 of the same applicant and no simple converting circuit has yet been realized. In effect, the above U.S. patent requires shifters 38 and 42 (FIG. 6) in order to rearrange the variable length code every predetermined bits in parallel, thus increasing the hardware. Therefore, it has been desired to attain the above advantage of the variable length code scheme with a simplified converting circuit.